1. Field of the Invention
The invention relates generally to performing trace on a system-on-chip (SOC), and more specifically, to storing trace information.
2. Related Art
System-on-chip devices (SOCs) are well-known. These devices generally include a processor, one or more modules, bus interfaces, memory devices, and one or more system busses for communicating information. Because multiple modules and their communications occur internally to the chip, access to this information is generally difficult when problems occur in software or hardware. Thus, debugging on these systems is not straightforward. As a result of development of these SOCs, specialized debugging systems have been developed to monitor performance and trace information on the chip. Such systems typically include dedicated hardware or software such as a debug tool and debug software which accesses a processor through serial communications.
However, debugging an SOC generally involves intrusively monitoring one or more processor registers or memory locations. Accesses to memory locations are sometimes destructive, and a data access to a location being read from a debugging tool may impede processor performance. Similarly, accesses are generally performed over a system bus to the processor, memory, or other module, and may reduce available bandwidth over the system bus for performing general operations. Some debugging systems do not perform at the same clock speed as that of the processor, and it may be necessary to slow the performance of the processor to enable use of debugging features such as obtaining trace information. By slowing or pausing the processor, some types of errors may not be reproduced, and thus cannot be detected or corrected. Further, accurate information may not be available altogether due to a high speed of the processor; information may be skewed or missing.
Some systems include one or more dedicated functional units within the SOC that are dedicated to debugging the processor, sometimes referred to as a debug unit or module. However, these units affect the operation of the processor when obtaining information such as trace information. These devices typically function at a lower speed than the processor, and thus affect processor operations when they access processor data. The debug system relies upon running debug code on the target processor itself, and this code is usually built into the debugee. Thus, the presence of the debug code is intrusive in terms of memory layout, and instruction stream disruption.
Other debugging systems referred to as in-circuit emulators (ICEs) match on-chip hardware and are connected to it. Thus, on-chip connections are mapped onto the emulator and are accessible on the emulator. However, emulators are prohibitively expensive for some applications, and do not successfully match all on-chip speeds or communications. Thus, emulator systems are inadequate. Further, these systems generally transfer information over the system bus, and therefore necessarily impact processor performance.
Another technique for troubleshooting includes using a Logic State Analyzer (LSA) which is a device connected to pins of the integrated circuit that monitors the state of all off-chip communications. LSA devices are generally expensive devices, and do not allow access to pin information inside the chip. In sum, there are many systems which are inadequate for monitoring the internal states of a processor and for providing features such as real-time state and real-time trace in a non-intrusive manner.
These and other drawbacks of conventional debug systems are overcome by providing a non-intrusive trace system which receives trace information from one or more processors or other devices. The trace system may include a first-in, first-out (FIFO) buffer which stores trace information. In one embodiment, the FIFO buffer is memory-mapped and is capable of being accessed by other systems without affecting processor performance. In one aspect of the invention, the trace system includes a trace buffer which receives information at an internal clock speed of the processor.
Non-intrusive methods are provided that specify what to do with trace information directly and do not interfere with processor operation. Specifically, the trace system includes devices which operate separately from the processor, operate at internal clock speeds of the processor, or operate in modes wherein the loss of trace information does not affect processor operation. Further, the trace information collected includes all of the information needed to perform trace operations; the processor does not need to be interrupted to obtain additional information, such as by a software program running on a debug tool. According to one aspect of the invention, the trace system is implemented in hardware associated with the processor, the hardware not requiring software intervention. In one embodiment, the trace information includes both address information and message information. In another aspect, the trace information includes timing information. In one aspect, the trace system may be used as a rate converter for converting a transmission rate of messages transmitted to a memory system on-chip or an external system.
In another aspect, the trace information may be compressed by the trace system. By compressing information, trace information is preserved for transmission over lower-bandwidth links and maximizes on-chip trace storage. For example, trace information may be compressed by compressing timestamp and address information. Further, trace information may be compressed by omitting duplicate types of information, such as one trace packet of a particular operation type. Also, information may be filtered by predefining criteria upon which trace information is generated. By filtering information and eliminating duplicate information on-chip, bandwidth requirements of links to external systems and on-chip storage requirements are reduced. A trace message may be compressed by replacing an absolute value of a data field in the message with a relative value. Periodic reference messages including absolute values of compressed information may be provided to provide a reference for the relative value.
These and other advantages are provided by an integrated circuit comprising at least one processor; a debug module operatively connected to the processor, the debug module including a FIFO buffer wherein the debug module is configurable by a user to store trace information produced by the processor in one of the following modes: a mode wherein the FIFO buffer is configured as a circular buffer; a mode wherein the debug module stops storing trace information when the FIFO buffer is full; and a mode wherein the debug module discards additional trace information when the FIFO buffer is full.
In one aspect, the debug module provides an indication to the processor that the FIFO is approaching a full level. The debug module may, for example, provide the indication within a finite number of storage locations from the full level of the FIFO. In one aspect, in the mode wherein the debug module stops storing trace information when the FIFO buffer is full, the integrated circuit generates an interrupt to disable storing of trace information or the generation of trace information. The integrated circuit may also execute handler code that accepts the interrupt and disables the storing of trace information or the creation of trace information, or empties the FIFO such that additional trace information can be stored. Alternatively, a software system may be provided that allows a user to manually inspect contents of the FIFO. In one aspect, the trace information includes address and message information.
In one aspect, the trace information is stored on byte-based boundaries. In one aspect, the trace information stored in the FIFO includes variable length messages. The trace information may also include a plurality of state information bits representing triggered conditions of the processor.
In one embodiment, storage locations of the FIFO are memory-mapped storage registers.
In one aspect of the invention, the FIFO receives trace information from a capture buffer operatively coupled to the processor. In one embodiment, the capture buffer is operatively coupled to the processor and other trace-generating devices by a bus separate from the system bus.
In one aspect, the debug module provides a control signal to the processor to stall execution of new instructions. In one aspect, the debug module provides the control signal to stall the processor in response to the capture buffer reaching a level of storage within a finite number of storage locations from the full level of the capture buffer. In one aspect, the debug module provides the control signal to stall the processor in response to the FIFO reaching a level of storage within a finite number of storage locations from the full level of the FIFO. In one aspect, the finite number of storage locations is greater than or equal to a number of trace messages that are capable of being produced by the stalled processor.
According to another aspect of the invention, an integrated circuit is provided comprising at least one processor; a debug module operatively connected to the processor, the debug module including a FIFO buffer wherein the debug module is configurable by a user to store trace information produced by the processor, and wherein the FIFO includes a plurality of memory-mapped registers configured to hold the trace information.
In one aspect, the FIFO operates in a mode wherein trace information is discarded when the FIFO buffer is full. In one aspect, the debug module provides an indication to the processor that the FIFO is approaching a full level. The debug module may also provide the indication within a finite number of storage locations from the full level of the FIFO.
In one aspect, the memory-mapped registers are read by a read circuit independent from the processor. According to another embodiment, the integrated circuit further comprising a system bus and wherein trace information is transmitted over a communication link separate from the system bus.
In one aspect, the trace information comprises at least one of program counter information; process identification information; address information; information stored in memory; and information related to a system bus transaction.
In one aspect, the trace information is stored in a RAM-based storage unit.
In one aspect, the trace information is stored in both RAM-based FIFO and the FIFO buffer.
According to another aspect of the invention, an integrated circuit chip is provided comprising at least one processor; a debug module operatively connected to the processor, the debug module including a first-in first out (FIFO) buffer wherein the debug module is to configurable by a user to store trace information produced by the processor; and an interface for transmitting trace information off-chip, wherein the trace information is stored in compressed format and transmitted off-chip. In one embodiment, the trace information is selectively transmitted to at least one of a memory circuit associated with the processor; and a link coupled to a debug system external to the debug module. In one aspect of the invention, the trace information includes an indication that one or more trace packets were lost. In another embodiment, the trace information includes an indication that the processor was stalled while generating the trace information.
In one aspect, the integrated circuit includes circuitry that compressed the trace information by representing at least one of an operand address, program counter, bus analyzer and instruction addresses as a signed address offset relative to the at least one address; and representing timing information by a time difference. In one embodiment, address offsets are determined by subtracting a previously sent address from a new address.
In one aspect of the invention, a method is provided for compressing trace information of a computer system, the method comprising steps of representing at least one of an operand address, program counter, bus analyzer and instruction addresses as a signed address offset relative to the at least one address; and representing timing information by a time difference. In one embodiment, the trace information is generated by at least one processor and the method further comprises a step of sending a reference message including at least one of timing information representing a time state of a processor process; a program counter of the processor; and an address of a device of a system bus. In another aspect of the invention, a decompression method is provided which recovers absolute information from the time difference and/or relative address information and information received in previous trace messages.
In one aspect, absolute or relative encoding of at least one of address information and timing information generating header information for the trace information, the header including: type of trace message source of the trace message wherein the information of the source of the message may include at least one of an indication of a source module which generated the message an indication of a channel of the source module that generated the message. In one embodiment, the header includes an indication of whether the address information is absolute address information or relative address. In one embodiment, the relative address is a signed offset address. In one aspect, the timing difference information represents a number of timer increments since a last reference trace message was generated. In one aspect, the trace information includes data written to memory of the computer system.
Further features and advantages of the present invention as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals indicate like or functionally similar elements. Additionally, the left-most one or two digits of a reference numeral identifies the drawing in which the reference numeral first appears.